1. Field of the Invention
The present invention relates to a display element drive circuit and a display device and, in particular, the present invention relates to an organic EL element drive circuit, which can reduce power consumption by restricting a feed-through current of a CMOS output stage of a current drive circuit for current-driving an organic EL element and an improvement of an organic EL display device.
2. Description of the Prior Art
It has been known that an organic EL display device, which realizes a high luminance display by spontaneous light emission, is suitable for a display on a small display screen and the organic EL display device has been attracting public attention as the next generation display device to be mounted on a portable telephone set, a PHS, a DVD player or a PDA (Personal Digital Assistants), etc. Known problems of such organic EL display device are that, since, when it is driven by voltage as in a liquid crystal display device, luminance variation thereof becomes substantial and that, since there is difference in sensitivity of organic EL element between R (red), G (green) and B (blue), a control of luminance of a color display becomes difficult.
In view of these problems, an organic EL display device using current drive circuits has been proposed recently. For example, JPH10-112391A discloses a technique in which the luminance variation problem is solved by employing a current drive system.
An organic EL display panel of an organic EL display device for a portable telephone set, a PHS, etc., having 396 (=132×3) terminal pins for column lines and 162 terminal pins for row lines has been proposed. However, there is a tendency that the number of column lines as well as row lines is further increased.
An output stage of a current drive circuit of such organic EL display panel of either the active matrix type or the passive matrix type includes a current source drive circuit, such as an output circuit constructed with a current mirror circuit, for each of the terminal pins. In, for example, U.S. patent application Ser. No. 10,102,671, which corresponds to JP2002-82662 claiming domestic priorities of JP2001-86967 and JP2001-396219, a drive stage includes a parallel-driven current-mirror circuit (reference current distribution circuit) having output side transistors the number of which corresponds to the number of terminal pins and drives the output circuit by generating a corresponding number of mirror currents on the basis of a reference current supplied from a reference current generator circuit provided precedent to an input of the drive stage and distributing these mirror currents to the respective terminal pins. Alternatively, the mirror currents distributed to the terminal pins are amplified by k times (k is an integer equal to or larger than 2) and drive the output circuits. The k-time amplifier circuit is disclosed in JP2002-33719 assigned to the assigned to the assignee of this application, in which a D/A converter circuit is provided for each terminal pin. In the k-time amplifier circuit, the D/A converter circuits corresponding to the respective column side terminal pins receive display data and column side drive currents for the respective terminal pins are generated simultaneously by A/D converting the column data.
It is general, in the organic EL display device, that one of the column side (anode side of the organic EL element) lines becomes the current discharge side and the row side (cathode side of the organic EL element) lines becomes the current sink side. Drive currents from the column side current drive circuits are supplied to the anode side of the organic EL elements (referred to as “OEL elements”, hereinafter) correspondingly to the row side scan. The cathode side of the OEL element is grounded through CMOS push-pull circuits to sink the drive currents.
Since the OEL element is a capacitive element, a portion of the drive current is accumulated in the OEL element as electric charge. Therefore, in the display device having matrix-arranged OEL elements, charges may flow from the OEL elements arranged in the peripheral portion, which are not to be scanned into the OEL element, which is to be scanned. Consequently, there is a problem that the OEL elements, which are not scanned, emit light and/or the luminance of the driven OEL elements varies, resulting in erroneous light emission.
FIG. 4 schematically shows a general organic EL display panel 1 of an organic EL display device. The organic EL display panel 1 includes matrix-arranged OEL elements 4, column side current drive circuits 2 and row side drive circuits 3. In FIG. 4, the OEL elements 4 are shown as capacitors and a CMOS push-pull circuit of the drive circuit 3 is shown as a pair of series-connected switches, for convenience.
In the organic EL display panel 1, in order to improve the luminance of the OEL elements and to prevent the luminance thereof from being varied, the OEL elements 4 are preliminarily charged for a constant time, which is determined by the junction capacitances of the OEL elements 4. Therefore, switch circuits SW each provided between the column side current drive circuit 2 and the ground line are made ON for a constant time before the drive is started, to discharge electric charges of the OEL elements 4 to thereby reset the OEL elements. The resetting of the OEL elements is performed by making the switch circuits SW ON for an initial constant time for which a row side line of the row side drive circuit 3, which is to be scanned, becomes low (L) level to ground anode side lines (column lines) X1, X2, X3, . . . connected to outputs of the current drive circuits 2. Thus, residual charge of the OEL elements 4 is discharged and, thereafter, the output currents of the column side current drive circuits 2 are supplied to the OEL elements 4. In the row side drive circuits 3, the OEL elements 4, which are to be not scanned, are reverse-biased. Otherwise, the drive current flows in the OEL element 4, which is to be scanned, also flows into other OEL elements arranged around the OEL element 4, causing the erroneous light emission. Therefore, the cathode side lines (row lines) Y1, Y2, Y3, . . . , which are to be scanned, are fixed to high (H) level.
As shown in FIG. 5, a level shifter 5 of the CMOS push-pull circuit of the row side drive circuit 3 receives a logic signal having logic values “L” level and “H” level, which are about 0V and 3V, respectively, or “1” and “0”, respectively, and generated according to a vertical scan through a gate circuit, etc., (not shown). The logic signal is level-shifted to about 0V and 20V by the level shifter 5 and the level-shifted logic signal having “H” and “L” levels is inputted to an inverter 7 of an input stage of the output circuit 6 and drives a CMOS output stage 8, which operates by a voltage (=20V) of the high power source line 9 (+Vcc) through the inverter 7. Incidentally, reference numeral 8a is an output terminal of the CMOS output stage 8, which is connected to a row side scan line Yi.
In this case, since a P channel transistor Tr1 in an upstream side reverse-biases the OEL element 4, its ON resistance is as high as, for example, several hundreds ohms and a parasitic capacitance C1 between a gate and a source thereof is small.
The parasitic capacitance between the gate and source thereof or a parasitic capacitance between the gate and a substrate has a substantial influence as a gate input capacitance. Therefore, the gate input capacitance will be described with reference to the parasitic capacitance between the gate and the source as a representative.
On the other hand, since a downstream side N channel transistor Tr2 receives a drive current from one of the OEL elements 4 connected to the row line, an area size thereof is large and its ON resistance is as small as several ohms. Therefore, the parasitic capacitance C2 between a gate and a source thereof becomes large correspondingly.
If the downstream side transistor Tr2 has such large parasitic capacitance C2, a transition characteristics thereof when the transistor Tr2 is changed from ON to OFF becomes gentle and, therefore, there is a problem that, when the upstream side transistor Tr1 is turned ON, a feed-through current flows from the power source line 9 to ground GND through the transistor Tr1 and the turned OFF transistor Tr2.
Since the power source voltage of the power source line 9 is as high as about 20V, the feed-through current becomes as large as several tens mA, causing power consumption to be increased together with risk of destruction of the driver IC.
Since the parasitic capacitance C2 of the transistor Tr2 in the row side drive circuit 3 having the transistors Tr1 and Tr2 having substantially different size ratio (area ratio of the gate to the source) is large, the usual countermeasures for the feed-through current by providing resistors and/or bypass circuit, etc, is not enough.